Staff Engineer (E4) – HBM PE Component Validation (Singapore)

Location: Singapore – Micron Campus, North Coast Drive
Team: HIG – HBM Product Engineering (PSE), Component Validation
Employment Type: Full-time, Individual Contributor

About the Role

As a Staff Engineer, you will be a senior technical authority who owns complex validation scopes, optimizes test flows, and leads technical problem‑solving for next‑generation HBM products. You’ll drive coverage completeness, improve detection efficiency, and mentor junior engineers—ensuring flawless product readiness through deep platform, Verilog simulation, and analysis expertise.

Key Responsibilities

• Validation Execution

• Lead end‑to‑end Validation Run execution in a high‑pressure, fast‑paced environment, ensuring on‑schedule starts/completions, risk‑aware re‑plans, and efficient IQP/ETV material usage.

• Own time‑bound data crunching pipelines (automated log parsing, metrics aggregation, anomaly ranking) and deliver decision‑ready summary reports and sightings by agreed Cycle Time.

• Guarantee coverage completeness across MBIST and Native flows; drive Hot/Cold corners, TSV screen/AQLK, async timing boundary coverage, and evidence‑backed closure.

• Platform Leadership

• Develop and debug test programs on ATE; enforce code quality, reviews, and release discipline.

• Align hardware configs (handler, socket, loadboard, probe card) to test intent and throughput targets.

• Advanced Analysis, Verilog Simulation & Automation

• Perform power/thermal characterization; correlate IDD/thermal data with performance/reliability; author recommendations for content changes and silicon fixes.

• Architect and execute Verilog simulations (bench creation, stimulus, checkers, waveform analysis) to replicate platform sightings, validate hypotheses, and de‑risk content changes before deployment.

• Build automation scripts and dashboards for anomaly detection, trend analysis, and coverage auditing.

• Debug & Continuous Improvement

• Lead silicon debug across Design, Verification, Quality, and System Engineering; drive corrective action closure with clear root‑cause evidence.

• Implement cycle‑time optimization strategies (parallelization, smarter sampling, content pruning, throughput tuning).

• Contribute to DFMEA gap closure and codify “Definition of Success” for validation quality.

• Mentorship & Collaboration

• Coach junior engineers on validation best practices, platform nuances, simulation methodology, and reporting standards.

• Partner with global teams for material readiness and platform enablement.

Minimum Requirements

• Bachelor’s in Electrical or Computer Engineering (or related).

• 5+ years in DRAM/HBM/NAND validation or product engineering.

• At least 2 years of HBM Validation experience.

• Test platform code development in C/C++, Python, and APG (Algorithmic Pattern Generator).

• Hands‑on experience with ATE for example for MBIST  and Native Mode (Advantest V93K) testing/debug.

• Proven ability to execute validation runs and perform high‑speed I/O validation with eye/IDD characterization.

• Experience defining shmoo targets, async timing boundaries, and coverage‑driven acceptance criteria.

• Verilog simulation experience (writing testbenches, running sims, stimulus/checkers, waveform/log analysis, correlation to platform behavior).

• Familiarity with high‑speed I/O validation and power/thermal characterization.

• Proficiency in scripting (Python/Perl) and data analysis tools; strong communication and presentation skills.

• Advanced scripting and data analytics skills; Confluence/Jira and Git/Perforce experience.
  

  Additional Skills

  • Familiarity with automation and ML‑driven validation workflows (e.g., anomaly classifiers, trend predictors).