Job Description

• Responsible to perform transistor level Static Timing Analysis (Synopsys Nanotime) for complex custom design and mixed signal circuit
• Responsible for developing timing models (NLDM, CCS and LVF) for advanced technology nodes mixed signal circuits and complex standard cells.
• Responsible for working with internal stakeholders to tune stop cell hierarchy level and to enable timing characterization.
• Responsible for developing and updating quality check utilities to ensure quality of timing models.
• Engage with various teams to understand new STA requirements.
• Maintenance of the timing model databases.
• Evaluate best in class EDA tools and flow in the industry.

Requirements

• Degree in Communications/Electronics/Electrical Engineering
• Usage of STA tools for timing analysis, characterization, library generation for Custom design or Mixed Signal Design.
• Have a solid understanding of MOSFET electrical characteristics and experience with transistor level circuit simulators, such as HSPICE and SPECTRE.
• Understanding of layout at the transistor level to effectively work with the mask design team
• Familiarity with reviewing DRC and LVS results an added plus.
• Understanding or an ability to learn a wide variety of industry standard modeling formats including Liberty (CCS, NLDM and LVF), Verilog, LEF, Milkyway, NDM, CLIB and SPICE.
• Familiar with working in Linux environment, load sharing concepts (such as LSF) and version control (such as ICM) an added plus
• Experience designing or a solid understanding of standard cell architectures, including state retaining elements like latches and flops is an advantage.

Ethos Search Associates - EA No: 13C6655
Rose - Reg No: R1109557