Position: Senior Scientist

Position Role: Process Integrator for Advanced Package Assembly for Heterogeneous Integration

The Advanced Packaging Program at the Institute of Microelectronics (IME) is seeking a passionate and skilled Scientist or Senior Scientist to join our team. This role is pivotal in advancing the state-of-the-art chip-to-wafer/chip-to-chip fine pitch micro-bump thermal compression bonding and chip-to-wafer fusion/hybrid bonding, underfilling and moulding capabilities, developing 2.5D interposer and 3D chip stacking assembly process integration flows for Heterogeneous Integration of chiplets. The position provides an exciting opportunity to contribute to groundbreaking technologies and collaborate with a dynamic team of researchers and external ecosystem stakeholders.

Key Responsibilities

• Lead flip chip bonding process capabilities development to scale down micro bump bonding and chip-to-wafer hybrid bonding technologies for heterogeneous chiplets integration.
• Develop assembly process integration approaches to realise complex novel system-in-package architectures by integrating chiplets.
• Work with design and wafer process integration teams to establish assembly process design rules for advanced packaging platform technologies.
• Identify the capability needs for future package architectures to conceptualise and lead assembly capability development projects involving new materials, advanced process integration approaches, and innovative concepts.
• Engage and manage internal and external stakeholders for project activities execution, and provide updates on schedule and deliverables
• Act as a subject matter expert (SME) for both internal and external stakeholders, providing guidance and expertise.
• Collaborate with cross-functional teams such as design, unit process team, yield improvement, and external partners, including materials, equipment, customers and universities, to identify technology gaps, define technology roadmap and drive the development.
• Develop new IPs and strengthen the advanced packaging IP portfolio in assembly processes and assembly integration approaches.
• Inspire and mentor students in semiconductor technology, contributing to workforce development in advanced packaging.
• Customer/partner engagement: ability to present technical content to customers and senior stakeholders; drive joint development (JDP/NRE).
• Mentoring junior engineers, influencing without authority, and ownership of module roadmaps.
• Willingness to be hands-on in the cleanroom and learning new processes and metrology equipment.

JOB REQUIREMENT/Qualification

Candidates should meet the following criteria:

• PhD in Materials Science & Engineering, Mechanical, Chemical, Electronics/ Electrical & Computer Engineering, Physics, Chemistry or a closely related field.
• 5-10 years of experience in the semiconductor industry, with expertise in package assembly processes and exposure to advanced package assembly technologies such as thermal compression bonding, chip-to-wafer bonding, underfilling, etc.
• Broad hands-on knowledge of one or more unit processes—such as wafer thinning, dicing, flip chip bonding, underfilling, solder ball attachment, wafer-level compression moulding - is preferred.
• Proven ability to work effectively in a diverse, matrixed environment and collaborate with cross-functional departments.
• Strong analytical/problem-solving skills (Ishikawa, Seven Basic Quality Tools, brainstorming) and proficiency with DOE and SPC (JMP/Minitab).
• NPI to HVM ramp experience: process window definition, control plans, and yield/cost improvement through pilot to high-volume manufacturing (foundry/OSAT).
• Reliability & standards: working knowledge of JEDEC/IPC/JESD (e.g., HTS, TC, HAST, BLR, EM), and failure analysis flows (X-ray, CSAM, FIB/SEM-EDX).
• Excellent written and verbal communication abilities.
• Demonstrated ability to manage multiple projects and priorities in a research and translational environment.
• Able to work effectively with multi-ethnic, multicultural teams and to build inclusive, high-performing teams.
• Proven ability to author impactful conference/journal papers and deliver presentations at international conferences (e.g., ECTC, IEDM, VLSI Symposia) across North America, Europe, and Asia.

What We Offer

• The opportunity to work on cutting-edge research projects in advanced packaging and heterogeneous integration.
• A collaborative & interdisciplinary work environment and access to state-of-the-art facilities and resources.
• File intellectual property (IP) promptly for new research findings.
• Publish research in peer-reviewed journals and present findings at international conferences.
• Researchers have access to advanced laboratories and characterisation equipment, fostering innovation and enabling the development of groundbreaking technologies. The institute encourages interdisciplinary collaboration and offers opportunities for professional growth and development.

Join us in shaping the future of semiconductor technologies and heterogeneous integration. Apply today!