Key Responsibilities:

1. Si-based 3D DRAM:

1) Novel Metals & Interconnect Strategy:

• Lead the research and integration of advanced low-resistivity conductive materials for sub-10nm metal line and interconnect applications.
• Focus on materials screening, physical property optimization (e.g. thermal stability and work function engineering), process optimization, and HVM readiness evaluation and preparation.

2) Advanced Junction Formation:

• Define the process for ultra-scaled junction formation.
• Develop low-thermal-budget process and technology to achieve precise doping profiles and activation, ensuring optimal device performance in HAR 3D structures.
• Develop novel characterization technologies for precise junction profile measurements in complex 3D structures.

3) 3D Architecture & Silicide Integration:

• Overcome challenges in high aspect ratio structures.
• Develop robust n-type silicide processes for complex 3D geometries, ensuring low contact/barrier resistance, high step coverage, high thermal stability, and future scalability in deep trench/via applications.

2. DRAM with novel channel oxide materials:

• Development of novel DRAM array memory architecture.
• Research and development of novel DRAM transistor channel materials.
• Novel device design and performance optimization.
• Research and development of key processes and process integration technologies.
• Development of TEG design, peripheral circuit design, and structural/electrical testing solutions.
• Materials, process, and device simulation.

Required Qualifications:

1. Education: Master's degree or above (PhD preferred).
2. Major: Physics, material science & engineering, chemistry.
3. Other Requirements:

• 8+ years of DRAM memory development experience, including at least 5 years as architecture or key technology lead.
• Familiar with TLC/QLC/PLC multi-bit memory mechanisms and their challenges to read/write algorithms, ECC, and wear leveling.
• Excellent systems thinking and cross-domain integration capabilities, able to efficiently coordinate circuit, device, firmware, verification, testing, and product teams.
• Excellent technical documentation writing and technical decision-making communication skills.
• In-depth understanding of the ECC architecture (BCH/LDPC) and DRAM controller collaboration mechanism is preferred.
• Familiarity with the impact of reliability modeling under advanced processes (such as TDDB, HCI, RTN) on the architecture.
• Publication of DRAM-related papers at international conferences (such as ISSCC, VLSI, IMW) is a plus.