•    Perform electromagnetic extractions on interconnects in IC Packages and PCBs, using tools such as Ansys HFSS, Q3D, SIWave, etc.,

•    Perform signal integrity circuit simulations on parallel digital interfaces such as DDR, analog SerDes channels and Power Delivery Networks (PDN), using tools such as ADS, Ansys Designer or HSpice.

•    Work closely with IC Package Design engineers for electrical design optimization of Packaging Interconnects and PDN

•    Work closely with IP owners, chip leads, package and PCB design engineers to optimize Bump/Ball maps of IPs and SoCs and to verify that the package electrical performance meets intended system impact targets

•    Perform frequency and time domain lab measurements on silicon die, bare substrates, PCBs and systems, often using micro probe stations

•    Contribute to the documentation of the simulation / extraction flows and Design Guidelines 

•    Interface with substrate and assembly suppliers through the packaging team, to help drive packaging technology improvement for electrical performance, such as 2.5D Integration and Substrates for high-speed applications

•    MS in EE with 6+ years of experience or Ph.D. in EE with 3+ years of experience or BS in EE with 8+ years of experience in Signal Integrity / Power Integrity Analysis and Interconnect Design Optimization for Electrical Performance 

•    Solid knowledge in Interconnect Electromagnetics, Transmission Line Theory and Circuit Theory

•    Power user of Ansys HFSS, Q3D, SIWave and/or Cadence Sigrity Power SI

•    Power user of Ansys Designer, HSpice or Agilent ADS

•    Working knowledge of Cadence APD and AutoCAD

•    Hands-on lab measurement experience with VNA, TDR System & Oscilloscopes, preferably with micro-probe stations

•    Strong communication, analytical and organizational skills; attention to details in engineering analysis and project management