• Utilize commercial and in-house EDA tools (e.g. Synopsys, Cadence, Siemens) for the design and implementation of 100 ~ 400 million gate integrated circuits in 7nm/5nm/3nm/2nm process technologies.
• Able to handle a full RTL to GDS or Gates to GDS flow, inclusive of all construction stages (e.g. Placement, clock tree synthesis, detailed routing, physical verification, formal verification and timing analysis).
• Some knowledge of front end design and synthesis is advantageous
• Proficiency in UNIX/Linux and scripting languages, e.g. tcl, bash

Required Qualifications:

• Degree, Masters or PhD in Electrical/Electronics/Computer engineering.
• Minimum of 7 years or more experience in a relevant field.