Main Responsibilities

• Responsible for Design rule release, Design Rule check waivers, Mask and related DRC definitions, Mask review and sign off, Process Requirement Specifications, etc. for R&D and Production Designs

• Drive/Contribute to deliver key milestones starting from Project Kick Off till End of Life

• Collaborate with a network of stakeholders including Process Integration, Advanced Mask Design, Scribe & Frame, Layout & Design and Quality & Reliability to help direct development efforts for a new Advanced NAND generation

• Ensure the quality of DRCs (Design Rule Checks) released with appropriate reaction to deviation from established design rules and proper documentation

• Work with Yield Enhancement, Product Engineers, Defect analysis, and Quality Assurance teams to understand process issues related to the database layout, and prioritize development of solutions with Process Integration, Advanced Mask Design, Scribe & Frame, Layout & Design

• Help design and evaluate test structures to provide data for next generation devices and to quantify process margin on current devices

• Summarize complex problems, derive, and explain actions taken to address them

• Drive effective multi-functional communication on issue resolution, and support across node Design Rule alignment

• Define sub-milestones for the project within the layout schedule and work with the various teams to achieve the targets and timelines

• Ensure the best possible communication between NAND Design Rule and other key stakeholders

• Enthusiastically identify and address process issues and process window vs. die size conflicts stemming from specific database layout or layout techniques

• Assure timely documentation and feedback of R&D activities regarding design rule improvements to production parts still in design phase.

Requirements

• Master's Degree with at least 5 years of experience or, Bachelor's Degree with at least 8 years of experience in semiconductor industry in the areas Process Integration, Yield Enhancement, Product Engineering, Test Structure Development, or Unit Process Development

• Exposure to design & layout, ability to do minor layout and experience with CAD tools like Cadence Virtuoso, K2view, and Mentor Graphics DRV/RVE is highly desired

• Understanding of Advanced NAND process flow, as well as the function and purpose of major NAND components, such as BL sensing, Word-line driver, CMOS under array, etc.

• Familiarity with CAD group interactions, data post-processing, and the process of transferring data from the database to the reticle