About Us

SerdesWorks is a deep-tech semiconductor startup focused on developing high-performance SerDes and interface IP solutions for next-generation data communication systems, including PCIe, UCIe, MIPI, DDR, and high-speed chiplet interconnects.

We are building advanced PHY and digital subsystems in TSMC advanced nodes (22nm / 12nm and beyond), targeting applications in AI compute, data centers, storage, and mobile platforms.

Role Overview

We are seeking a highly motivated RTL / Digital Design Engineer to develop and implement high-speed interface digital subsystems (PCS / controller logic) for SerDes and PHY IP.

You will work closely with analog designers, system architects, and verification engineers to deliver production-quality IP.

Key Responsibilities

1. RTL Design & Architecture

Design and implement RTL for PHY PCS (Physical Coding Sublayer) and digital control blocks

Develop modules for:

- Encoding/decoding (e.g., 8b/10b, 128b/130b, 256b/257b)

- Lane alignment and deskew

- Elastic buffers and clock domain crossing (CDC)

- Link training and state machines (e.g., LTSSM for PCIe, MIPI state machines)

- Translate system-level specifications into synthesizable Verilog/SystemVerilog

2. Integration with Analog PHY

Interface digital logic with analog front-end (PLL, CDR, TX/RX, CTLE)

Define and implement:

- Digital-analog control interfaces

- Calibration and adaptation loops

- Support mixed-signal simulation (AMS co-sim)

3. Verification & Validation

Collaborate with verification team on:

- Testbench development (UVM preferred)

- Functional coverage and corner-case validation

Perform:

- RTL simulation (VCS/Xcelium)

- Lint, CDC, and reset domain checks

- Debug functional and timing issues

4. Synthesis & Implementation Support

Ensure RTL is optimized for:

- High frequency (multi-GHz operation)

- Low latency and power efficiency

Work with backend team on:

- Timing closure

- Area/power trade-offs

5. Compliance & Standards

Implement designs compliant with:

- PCIe Gen5/Gen6

- MIPI C-PHY / D-PHY / M-PHY

- UCIe / DDR interfaces

- Participate in compliance verification and interoperability testing

Requirements

Bachelor’s / Master’s in Electrical Engineering / Computer Engineering

≥ 3 years experience in digital IC / RTL design

Strong proficiency in:

- Verilog / System-Verilog

- Digital design fundamentals (FSM, CDC, pipelining, timing)

Experience with:

- RTL simulation tools (Synopsys VCS / Cadence Xcelium)

- Lint and CDC tools (SpyGlass / Jasper / Questa CDC)

Preferred (Strong Advantage)

Experience in high-speed interface / SerDes / PHY design

Knowledge of:

- PCIe / MIPI / DDR / Ethernet protocols

Familiarity with:

- UVM verification methodology

- Synthesis tools (Design Compiler / Genus)

Understanding of:

- Clocking architectures (PLL/CDR interaction)

- Low-power design techniques