Job Description

• Undertake the roles of a custom layout engineer in realizing the physical implementation of a variety of circuitries, including Foundation IP(Standard Cells, Memory Compilers, IO/ESD), Analog IP, and RF building blocks.
• Be responsible for tasks assigned and assume full responsibility of the complete layout implementation process, including floor planning, layout construction, physical verification and QA flow sign-off.
• Provide timely project status updates and proactively anticipate potential execution pitfalls to ensure high-quality and on-time delivery foreach project.       
• Be proactive in communicating effectively.

Job Requirements

• Bachelor’s Degree in Electrical, Electronic, or Material Science Engineering.         
• With more than 8 years’ experience in custom IC layout for IO/ESD libraries using advanced finFET/GAA process nodes.
• Strong knowledge in floor-planning techniques at different hierarchies, with emphasis on power mesh planning, critical block placement,critical signal routing and top-down integration flow.         
• Proficient in understanding DRM of advanced CMOS technologies and have a good grasp of deep sub-micron and DFM issues for high-performance layout designs.
• Analytical and skillful in debugging physical verification checks (e.g. DRC/LVS/ERC, etc.).
• Proficient in Synopsys/Cadence layout editor and physical verification tools.        
• Team player and effective in cross-team communication and time management.         
• Scripting skills in languages such as Python, Tcl, Perl, or C-shell are a plus.         
• Candidates with strong Analog/RF experiences are welcomed to apply.

Interested candidates may apply through the application system. We regret to inform only Shortlisted candidates will be notified.

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