Key Responsibilities:

• Develop and implement micro-architecture for complex digital blocks.
• Write synthesizable RTL code in Verilog/SystemVerilog for various IPs and SoCs.
• Perform linting, CDC (Clock Domain Crossing), and low-power checks (UPF/CPF).
• Conduct logic synthesis, timing constraints generation, and timing closure support.
• Collaborate with verification engineers to define test plans and ensure design quality.
• Support pre-silicon validation and post-silicon bring-up and debug activities.
• Create and maintain technical documentation.

Qualifications and Skills:

• Bachelor’s or Master’s degree in Electrical/Electronics Engineering or a related field.
• Proven experience in ASIC design flow and methodologies.
• Strong proficiency in RTL coding using Verilog or SystemVerilog.
• Hands-on experience with synthesis, timing analysis, and scripting languages (e.g., TCL, Python).
• Knowledge of low-power design techniques and power integrity issues is a plus.
• Familiarity with industry-standard EDA tools from Synopsys, Cadence, or Siemens.
• Excellent problem-solving skills and a strong team-oriented mindset.
• Effective communication skills and the ability to work in a dynamic, global team environment.